代表性论文专著
[1] Roemer C, Dersch N, Darbandy G, Schwarz M, Han Y, Zhao Q-T, et al. Physics-based compact current model for Schottky barrier transistors at deep cryogenic temperatures including band tail effects and quantum oscillations. Solid State Electron 2024;212:108846.
[2] Sun J, Han Y, Junk Y, Concepción O, Bae J-H, Grützmacher D, et al. Low contact resistance of NiGeSn on n-GeSn. Solid State Electron 2024;
[3] Bestelink E, Galderisi G, Golec P, Han Y, Iniguez B, Kloes A, et al. Roadmap for Schottky barrier Transistors. Nano Futur 2024.
[4] Han Y, Sun J, Bae J-H, Grützmacher D, Knoch J, Zhao Q-T. High Performance 5 nm Si Nanowire FETs with a Record Small SS= 2.3 mV/dec and High Transconductance at 5.5 K Enabled by Dopant Segregated Silicide Source/Drain. 2023 IEEE Symp. VLSI Technol. Circuits (VLSI Technol. Circuits), IEEE; 2023, p. 1–2.
[5] Liu M, Junk Y, Han Y, Yang D, Bae JH, Frauenrath M, et al. Vertical GeSn nanowire MOSFETs for CMOS beyond silicon. Nature Commun Eng 2023;2:7.
[6] Han Y, Sun J, Radu I, Knoch J, Grützmacher D, Zhao Q-T. Improved performance of FDSOI FETs at cryogenic temperatures by optimizing ion implantation into silicide. Solid State Electron 2023;208:108733.
[7] Knoch J, Richstein B, Han Y, Frentzen M, Schreiber LR, Klos J, et al. Toward Low-Power Cryogenic Metal-Oxide Semiconductor Field-Effect Transistors. Phys STATUS SOLIDI A-APPLICATIONS Mater Sci 2023.
[8] Xi F, Grenmyr A, Zhang J, Han Y, Bae JH, Grützmacher D, et al. Heterosynaptic Plasticity and Neuromorphic Boolean Logic Enabled by Ferroelectric Polarization Modulated Schottky Diodes. Adv Electron Mater 2023;9:2201155.
[9] Yang D, Wirths S, Knoll L, Han Y, Buca DM, Zhao QT. Enhanced Device Performance with Vertical SiC Gate-All-Around Nanowire Power MOSFETs. Key Eng Mater 2023;945:77–82.
[10] Roemer C, Dersch N, Darbandy G, Schwarz M, Han Y, Zhao Q-T, et al. Compact modeling of Schottky barrier field-effect transistors at deep cryogenic temperatures. Solid State Electron 2023:108686.
[11] Han Y, Sun J, Xi F, Bae J-H, Grützmacher D, Zhao Q-T. Cryogenic characteristics of UTBB SOI Schottky-Barrier MOSFETs. Solid State Electron 2022;194:108351.
[12] Richstein B, Han Y, Zhao Q, Hellmich L, Klos J, Scholz S, et al. Interface Engineering for Steep Slope Cryogenic MOSFETs. IEEE Electron Device Lett 2022;XX:1–1.
[13] Xi F, Han Y, Grenmyr A, Grützmacher D, Zhao Q-T. Four-Terminal Ferroelectric Schottky Barrier Field Effect Transistors as Artificial Synapses for Neuromorphic Applications. IEEE J Electron Devices Soc 2022;10:569–74.
[14] Han Y, Xi F, Allibert F, Radu I, Prucnal S, Bae J-H, et al. Characterization of fully silicided source/drain SOI UTBB nMOSFETs at cryogenic temperatures. Solid State Electron 2022;192:108263.
[15] Han Y, Sun J, Richstein B, Allibert F, Radu I, Bae J-H, et al. Steep Switching Si Nanowire p-FETs With Dopant Segregated Silicide Source/Drain at Cryogenic Temperature. IEEE Electron Device Lett 2022;43:1187–90.
[16] Xi F, Han Y, Liu M, Bae JH, Tiedemann A, Grützmacher D, et al. Artificial Synapses Based on Ferroelectric Schottky Barrier Field-Effect Transistors for Neuromorphic Applications. ACS Appl Mater Interfaces 2021;13:32005–12.
[17] Han Y, Xi F, Allibert F, Radu I, Prucnal S, Bae J-H, et al. Impact of the backgate on the performance of SOI UTBB nMOSFETs at cryogenic temperatures. 2021 Jt. Int. EUROSOI Work. Int. Conf. Ultim. Integr. Silicon, IEEE; 2021, p. 1–4.
[18] Han Y, Li Y, Song Y, Chi C, Zhang Z, Liu J, et al. A comparative study of selective dry and wet etching of germanium–tin (Ge1− xSnx) on germanium. Semicond Sci Technol 2018;33:85011.
[19] Han Y, Song Y, Chen X, Zhang Z, Liu J, Li Y, et al. Abnormal strain in suspended GeSn microstructures. Mater Res Express 2018;5:035901.
[20] Zhang ZP, Song YX, Li YY, Wu XY, Zhu ZYS, Han Y, et al. Effect of thermal annealing on structural properties of GeSn thin films grown by molecular beam epitaxy. AIP Adv 2017;7.
[21] Zhang ZP, Song YX, Zhu ZYS, Han Y, Chen QM, Li YY, et al. Structural properties of GeSn thin films grown by molecular beam epitaxy. AIP Adv 2017;7.
[22] Zhu Z, Song Y, Zhang Z, Sun H, Han Y, Li Y, et al. Vapor-solid-solid grown Ge nanowires at integrated circuit compatible temperature by molecular beam epitaxy. J Appl Phys 2017;122.